Content addressable memories (“CAMs”) are commonly used in cache and other address translation systems of high speed computing systems. Ternary content addressable memories (“TCAMs”) are ternary state CAM cells and are commonly used for parallel search in high performance computing systems. The unit of data stored in a TCAM bitcell is ternary, i.e., having three possible states: logic one, logic zero, and don't care state (referred to as an “X” state). To store these three states, TCAM bitcells include a pair of memory elements.
CAMs permit its memory cells to be referenced by their contents. Thus, CAMs have found use in lookup table implementations such as cache memory subsystems and are now rapidly finding use in networking system applications such as network address translation, and other applications such as pattern recognition and data compression. A valuable feature of CAMs is its ability to perform a fast search operation in which search data is compared with stored data. Typically, a searched data word is loaded onto search lines and compared with stored data words in the CAMs. The stored data words are compared bit-by-bit with the searched data word. During a search-and-compare operation, the CAMs perform a parallel search and generates match or mismatch signal associated with each stored data word, indicating whether the search word matches any of the stored data words.
FIG. 1 illustrates a prior art block diagram for TCAM unit cells connected to a match line sense amplifier. TCAM bitcells 10 that form a data entry can be connected along the same row and connected to a match line ML. The bitcells 10 can also be coupled to word lines WLY and WLX, search lines ST and SC, and bitlines BC and BT. The word lines WLY and WLX run perpendicular to bitlines BC and BT. A match line sense amplifier 20 is connected to an end of the match line. Each of the TCAM bitcells 10 comprise two static random-access memory (“SRAM”) cells (or dynamic random access memory (“DRAM”) cells, depending on the implementation) and a compare circuit 12 (e.g., an XOR circuit) to compare the data within the respective TCAM bitcell with bits of the searched data word.
An indication of a match or mismatch is indicated on the match line. The compare circuits 12 of the TCAM cells 10 of a stored data word can have their respective outputs logically dotted together in a dot-XOR structure via the match line. If any of the compare circuits 12 are on (i.e., driving the match line to a low state to indicate a mismatch), a mismatch can be identified for that respective stored data word. If the match line goes to a high state, then the stored data word can be identified as a match and the location of that data entry is outputted.
FIG. 2 illustrates a prior art block diagram for compare circuits of TCAM bitcells connected to a match line sense amplifier. As indicated above, the compare circuits 12 of the TCAM data entry are connected together via the match line. Due to the large number of compare circuits 12, the match line can be highly capacitive. The match line is further coupled to the match line sense amplifier 20 at one end of the match line to charge the match line and sense the voltage on the match line. Due to the charging requirement for operation, the match line can consume large amounts of power. For this reason, TCAMs require relatively high power and large current pulses to operate the compare circuits and the match line sense amplifier.
FIG. 3 illustrates a prior art circuit for a match line sense amplifier. A match line sense amplifier 30 comprises a p-channel field effect transistor (“PFET”) 31 and an inverter 32. The PFET 31 is connected across the power supply Vdd and a match line. The inverter 32 inverts the signal ML of the match line to an inverted output signal OUT. The amplifier 30 has several drawbacks. First, the large voltage swing between ground and Vdd on the match line can cause large current burn off. Second, the amplifier 30 suffers from poor performance due to taking a long time to discharge the match line for single bit mismatches. Third, the search lines may also transition states for each search cycle that can cause more power burn.
FIG. 4 illustrates a prior art circuit for another match line sense amplifier from U.S. Pat. No. 7,724,559. In U.S. Pat. No. 7,724,559 (herein the “'559 patent”), the '559 patent has addressed such problems by charging the match line using an n-channel field effect transistor (“NFET”) to a voltage below the power supply voltage Vdd. A self-referenced sense amplifier 40 is coupled to the match line ML of a CAM to determine the state of the match line ML. The self-referenced sense amplifier 40 includes a PFET transistor 43 coupled in series to an NFET transistor 44 to connect ML to the power supply voltage Vdd. A sensing inverter 45 is coupled to the end of ML. The output of the sensing inverter 45 is fed back to the gate of NFET 44, while the gate of PFET 43 is coupled to a PREbar signal. A sensing inverter 46 is coupled to a sense node 47 between the PFET 43 and then NFET 44 to output the MLOUT determination. A keeper 48 is used to maintain that voltage on the match line.
Prior to operation, ML is set low, e.g., to ground, and precharge bar PREbar is set high, e.g., to Vdd. In operation, ML is precharged to the threshold (or trigger point) of the inverter 45, and, thereafter, ML sensing occurs. To begin precharging ML from its initial low, PREbar goes low from its initial high, which turns on the PFET 43. Because ML is initially set low, the gate of NFET 44 is set high by inverter 45, turning on NFET 44, whereby current flows to begin charging ML to the threshold of inverter 45. When the voltage on ML crosses the threshold of the sensing inverter 45, the sensing inverter 45 will start discharging the gate of the NFET 44 low until the NFET 44 turns off. As a result, the sense node 47, which was originally coupled to ML through NFET 44, uses the full charge provided by PFET 43 to charge node 47 to Vdd. This causes the output of the inverter 46 to discharge low to GND. Precharge bar PREbar is subsequently disabled by a signal from a one-bit miss reference ML (not shown). Moreover, the keeper 48 can be coupled between the gate of the NFET 44 and ML. The keeper 48 is provided to maintain the precharged value to prevent leakage on ML from being misinterpreted as a mismatch.
The '559 patent precharges the match line through the NFET 44. A drawback of such match line sense amplifier is that precharging of the match line is slow since the NFET 44 is in a source follower mode, i.e., overdrive of that NFET 44 is significantly reduced when the source of the NFET 44 goes up in voltage. Furthermore, it is well known that NFETs can only pull up as far as its Vgs voltage minus a threshold voltage. In doing so, the NFET 44 can only pull up to its threshold voltage before the NFET 44 turns off. The turn off of the NFET is asymptotic, which leads to a very slow charging of the match line by the NFET. Also, the NFET does not allow for overshooting since it cannot charge above the threshold voltage of the NFET.
Additionally, the sensing inverter 45 requires a Schmitt trigger since the sensing inverter 45 does not provide enough margin to combat the sensitivity of the system which may lead to tripping back and forth by the sensing inverter 45. The Schmitt trigger provides hysteresis to keep the inverter 45 in a current state unless the input is beyond the trip point to trip back to its other state. A drawback of using such sensing inverter 45 that has the Schmitt trigger is that the inverter 45 would require more complexity, and, in particular, additional transistors for implementing the Schmitt trigger.
For the foregoing reasons, there is a need for new methods and apparatuses for a sense amplifier that is self-referencing, provide adequate overshoot of the line voltage, reduce complexity, quickly charge a line to be sensed, and/or increase performance speed.